Refusal to take responsibility.
Hi, Just thought I would make a note here of your handling of my issues. I ordered a pair of HD6xx headphones and then earlier today recieved the package. I drive to go and get it, as I like in the UK I had to pay import tax and handling fees. These total £47.92. The breakdown being £35.92 in tax and £12 in fees. These taxes were calculated of the shipping label of the box, which marked the shipment as the 6xx headphones of $199 value. Before leaving the parcel depot, I open the box to find a $35 lord of the rings mousepad. So now the problem is not only do I not have the headphones, but you have marked the shipment wrong so I have paid £47.92 fees for the handling of the mousepad. Which would have acrued £0 of fees if marked correctly as it is under £135. I go back to the desk but as I have already paid the fees I am unable to reject the shipment, but as the box said 6xx, there was no way for me to know before opening it. I contact support and they offer me a replacement, which...
Jan 17, 2025
SPDIF Unlike asynchronous USB audio, a SPDIF (or toslink or AES3) signal contains an embedded clock that must be recovered by a receiver circuit. The quality of that recovered clock can vary widely depending on many factors. The design of the PLL (phase locked loop) used to synchronize the internal clocks for the d-a converter is critical to achieving high fidelity sound reproduction. The SPDIF receiver in the SDAC balanced is the AK4117 which is a solid performing hardware receiver circuit. The intrinsic jitter of the AK4117 PLL is not bad but since it is designed to acquire lock rapidly the PLL loop filter will not allow it to reject jitter in the audio band. For this reason we use a two stage clocking system with a second PLL that re-clocks the recovered clock from the AKM receiver. The second stage PLL is an extremely quiet digitally synthesized clock that has a loop bandwidth of 1Hz. This means that any incoming jitter on the SPDIF line that is above 1Hz will be attenuated dramatically to where it will not be able to produce any audible artifacts in the audio. To measure the effects of jitter on a DAC we send a relatively high frequency tone through the DAC and look for jitter modulated side bands in an FFT plot. I will upload a pictures of this that shows the output of the SDAC balanced reproducing an 11.025kHz tone with and without 1UI (177nS) of sinusoidal jitter. The SPDIF input is transformer-coupled for complete ground isolation. Note that the SPDIF interface maximum sample rate is 192kHz BALANCED LINE OUTPUTS The AK4452 DAC uses switched capacitor output filters (following the delta sigma modulator) which provide an inherently balanced signal at the output pins. From here, the balanced signal is sent to a fully differential output filter/driver amplifier. This amplifier has differential inputs and balanced outputs. Specifically this circuit is a fully differential multiple feedback 2nd order low pass filter with a Bessel response and a corner frequency of 100kHz. The fact that it is fully differential guarantees that the positive and negative phases leave the box with almost perfect amplitude matching (around +/-0.002dB). The Bessel response is chosen for the best phase response. The balanced outputs have a 300 Ohm output impedance (150 Ohms per leg) and produce exactly 2x the output voltage of the unbalance outputs at 4.34Vrms in to a 100k Ohm load. The unbalanced line outputs on the 3.5mm stereo jack operate simultaneously to the balanced outputs and put out 2.17Vrms in to a 100k Ohm load. All inputs and outputs feature robust ESD (electrostatic discharge) production. A note on balanced vs. unbalanced signals: First of all, there is no inherent difference in fidelity between a balanced and an unbalanced signal. Under ideal conditions both signals can carry identical information. It is the factors of the real world where there we can differentiate (pardon the term!) between the two. As many probably already know, balanced line signal transmission with a differential receiver can reject common mode noise. The amount of rejection is known as the common mode rejection ratio (or CMRR). An unbalanced interface is prone to noise caused by ground potential differences between a DAC and a downstream device. This can be caused, for instance, by a setup where a computer is connected to a DAC via USB, the DAC is then connected to an amplifier, and that amplifier is connected to earth ground. If the computer is also connected to earth ground then you have a ground "loop" and current will flow through the audio cable ground between the DAC and amp causing noise. A balanced interface can reject that noise but the design of the balanced driver and receiver circuitry can cause degradation to the signal in the form of distortion and amplifier noise. So you see there is no black and white way to evaluate whether balanced is better or worse in a given setup. Ideally the DAC would have a galvanically isolated (ground isolated) USB interface which would break the "loop". Galvanically isolated USB is expensive and unfortunately not in the budget for the SDAC. So in this case, if there is going to be a potential for a ground loop, a well designed balanced interface can really help. The CMRR of the receiving device will determine how well it will reject noise. USB Audio Class II For those with high resolution files the SDAC Balanced will play PCM sample rates up to 384kHz and DSD 256 This is driver-less operation on Mac OSX and current versions of Windows 10. For older versions of Windows USB I mode is required and then sample rates will be limited to 96kHz. Here are some performance plots and measurements from our pilot build of SDAC Balanced DACs. These figures are actual measurements. Guaranteed performance specifications will be more conservative.
Frequency response @ 96kHz Fs: DC-20kHz +/-0.03dB Frequency response @ 129kHz Fs: DC-48kHz +/-0.4dB All distortion measurements are with a 22-22kHz bandwidth THD+N% @ -0.15dBFS 44.1kHz 20Hz 0.0016 100Hz 0.0011 1KHz 0.0007 10KHz 0.0008
THD+N% @ -0.15dBFS 48kHz 20Hz 0.0018 100Hz 0.0012 1KHz 0.0008 10KHz 0.0007
THD+N% @ -0.15dBFS 88.2kHz 20Hz 0.0016 100Hz 0.0011 1KHz 0.0007 10KHz 0.0006
THD+N% @ -0.15dBFS 96kHz 20Hz 0.0018 100Hz 0.0012 1KHz 0.0008
10KHz 0.0006 THD+N% @ -0.15dBFS 176.4kHz 20Hz 0.0016 100Hz 0.0011 1KHz 0.0007 10KHz 0.0006
THD+N% @ -0.15dBFS 192kHz 20Hz 0.0018 100Hz 0.0012 1KHz 0.0008 10KHz 0.0006 Dynamic Range (A-Weighted) 115.4dB Dynamic Range (Un-Weighted) 112.3dB Crosstalk @ 1kHz, -10dBFS -120dB Crosstalk @ 10kHz, -10dBFS -112dB IMD CCIF, -6.03 dBFS, 19/20kHz, 24/96k 0.00015% IMD SMPTE -2 dBFS, 24/96k 0.0012% IMD SMPTE -6 dBFS, 24/96k 0.0008% Linearity @ -90dBFS +/-0.025dB Maximum output unbalanced 2.17V Maximum output balanced 4.34V
Thank you for these measurements!
I have a few questions regarding the spdif input if you don't mind: - My source has 110 ohms AES outputs with a 3.3V P-P voltage (or maybe a bit more). As this unit is transformer coupled I guess I can get away with a simple impedance matching voltage divider. What is your take on this? What is the maximum P-P voltage the spdif input can handle?
- Why did you choose to recover the spdif clock instead of using an ASRC to some high internal frequency like many other designs do nowadays (benchmark for example, or what ESS embeds in their DAC chips) ?
- I plan on using several DACs in a multiway active system, all fed from the same source and clock (miniDSP UDIO8, with 4 AES3 outputs). What kind of synchronization can I expect between different DACs in this situation? What will the maximum delay difference be? Is there a risk of a drift between units over time? In this situation I like the ASRC approach as it guaranties no drift over time and a synchronization that will stay within a sample of the target internal sampling frequency of the DAC. What about your approach in this regard?
Thank you :)
I like the simple AES/spdif conversion cable, I will definitely follow this path, thanks for taking the time to test this and post measurements!
Regarding the -40dB on/off click, it might potentially be a problem in my application as I am relying entirely on digital volume control, targeting around 120dB SPL/1m at 0dBFS (and 5dB(A) SPL residual noise with this particular DAC). In this scenario -40dBFS is still 80dB SPL. Not a big deal if I keep the DAC on all the time (it is less than 5W after all), as this will only happen on power failures or user errors. Still, as I will be connecting compression drivers directly I am concerned about the spectral distribution of that click. Does it have energy toward DC or is it band limited?
Look forward to testing one in the future.
Amir, Founder, Audio Science Review
Thank you
I would recommend setting the input sensitivity of your speaker systems such that the maximum SPL you desire is achieved somewhere around 0dBFS. I am assuming you don't desire, or have the ability to create, 120dB SPL:). This would put your nominal program material at somewhere around 20dB below that and the power on click at another 20dB below that. In other words, the click will be at a level significantly lower than normal program material. I will try to post a recording of the click somewhere so you can hear what it sounds like...
I will look that up.
on:
off:
I don't know what the rated max power handling of 476Mg is but the distortion plots in the K2.S9900 White Paper (source below) suggest it can handle 7.5V rms from 200Hz to 20kHz. At 200Hz the impedance is about 10.5 Ohms so that would be 5.3W which is about 1300 times more than the peak power of the SDAC power-off pulse. As for the 045Be driver, it has an impedance of around 4.3 Ohms in its pass-band. A system aligned for 0dBFS = 120dB SPL would result in almost 15W on that driver. Now it is super unlikely that music would ever contain enough power above 15kHz to actually cause damage, but an accidental test tone at full scale would. The -30dBFS pulse would, for about 40mS, dissipate 19 milliwatts. Again, the series capacitor will reduce this depending on its value. This discussion so far has used the peak value of the pulse in the full audio bandwidth. If you want to just consider the LF content of that pulse try this: Run the pulse through a 24dB/octave low pass filter at 200Hz. The peak value of this result is around -46dBFS. This means that at below 200Hz the pulse would dissipate 1/20,000th the power of full scale. This is 200 micro watts on the 476Mg and 1 milliwatt on the 045Be. Of course it is always best practice to turn on your power amplifier last when power up your system and turn it off first when powering your system down. Furman makes some inexpensive power sequencers that can automate this.
Hopefully the upstream playback and signal processing software is robust. In my opinion that is what poses the greatest risk to your drivers. Best, Michael PS. I found the white paper at: www.keithhaddock.com/assets/_managed/products/files/K2S9900WhitePaper1-6-09.pdf The 045Be impedance came from this chart : http://www.audioheritage.org/images/projectmay/driver-data/thumbs/1500al-435be-045be-imp.jpg
I think what rajapruk is concerned about is not power related, but excursion related: diaphragm fatigue than can occur with metal suspension diagrams.
I think a protection cap can take care of most of it. Here are for example the same FFT of the on/off clicks as above but with a 1st order 200Hz HP filter applied:
on:
off:
I think rajapruck wanted to ask about IMD vs level rather than THD vs level, in reference to the "intermodulation distortion versus level" measurement Amir routinely does on the ASR forum. This test shows strange behaviors with all last generation mobile ESS dacs (ESS "hump" in the -40dB to -20dB range) which is a concern when using digital level control. Example: https://audiosciencereview.com/forum/index.php?threads/review-and-measurements-of-wesiontek-khadas-tone-board-dac.4823/
Michael